EDA News ÿ€ Monday May 26, 2003 From: EDAToolsCafe _____ Meet Rob Lucke (Doctor Linux) at DAC! _____ About This Issue ÿ€ Down but not out in Silicon Valley A Panel discusses the nuances of business in the New Economy _____ May 19 - 23, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Things were definitely quiet when I made my way down to Silicon Valley recently to sit for an hour of conversation with three EDA executives on May 6th. It's hard to miss the blocks and blocks of empty office space as you drive through some of the industrial business parks in the South Bay. However, Tommy Eng, Vice Chairman at Terra Systems, George Janac, Vice President of Engineering, CTO and Founder of InTime Software Inc., and John Ford, Vice President of Marketing and European Sales at Virtual Silicon, are neither shying away from the realities of the current economic climate, nor throwing in the towel in frustration. On the contrary, all three of these guys seem steady, realistic, and quite determined to move forward despite the challenges. Silicon Valley has nothing to worry about in the long term, with folks like this driving the industry. We started by discussing 90 nanometers. Eng: "As far as I'm concerned, the industry is not doing 90 nanometers - or if they are doing it, they're not doing it happily. Most products coming off the line today are 0.18 micron. The remainder are at 0.13 micron, but we think by the end of the year, everything will be at 0.13 micron." Janac: "I think the main drivers for 90 nanometers right now are the FPGA guys. They're the ones who need it the most. The rest of the industry is only planning for what things will look like at 90 nanometers. Meanwhile, 0.18 represents about 20% of our business, with 0.15 or 0.13 micron being about 80%. But getting a high yield is still an expensive proposition when you're doing a 0.13-micron design." Ford: "We're doing 90 nanometers right now, and we have been at it for a year - although it represents under 10% of our business. We would characterize it as an [emerging] form of research. From a revenue standpoint, 013 micron has been a big node for us, although many of our customers are still working at 0.18 micron. Two years ago, everybody thought that we would all be at 0.13 by now - that it would be a big success. We were obviously way off. It's taken two years longer that we thought it would [to get 0.13 micron] up and running." Eng: "We believe Moore's Law is [a problem]. We're seeing today a situation where the physics is running ahead of the business [issues]. Traditionally, we've been going to the next node just because we can do it. And we had the attitude that if we built it, people would buy it. We had the money to do 0.13 micron - investment capital was cheap [just a couple of years ago]. But we've figured out that none of that is true any more. There's a relationship between economics and technology. We don't not believe in Moore's Law - but fundamentally it's insatiable, just like our consumer society. Eng's Law says: 'With every hardware upgrade, software performance slows by half and comes needing twice as much memory - every 18 months.' So, the question isn't, 'Can we afford Moore's Law?' The question is, "How can we make products and keep it affordable?' The business model and economic climate both say this is the question we have to apply to the technology." Janac: "As NRE costs have gone up, it's created an imbalance that has caused a shift to the FPGA side. ASIC or COT models are falling behind. Meanwhile, there's no 'buy' economy for IP that's been massively established - no efficient selling system that's been built up. All of this [may be] causing a shift to software, especially at 0.13 and below. We saw a similar situation in the PC world - it was a slow process to set up a component market. So now we're [back to] whether to make or buy, whether it's design software or IP." Ford: "From a physics standpoint, nanometer lives. From an economics standpoint, however, the [design and manufacturing processes] have been broken for two years. Ten years ago, nobody would have thought twice about moving down to the next process node. The economics of the move clearly paid out. But that all stopped at 0.13 micron, and it's not being fixed by moving to 90 nanometers. The economic downturn makes it simple - you can't spend $750,000 to make a mask and spend $25 million on a design team, only to come up with a dry well. So you're seeing a split in the market plan. FPGAs are clearly driving the technology at the foundries. It's costing a lot in area yields, but the wealthy companies are able to hang on [even in this economy] and they'll make money. So, here Ford's Law: 'In the future, everything is going to cost a buck.' Going forward, we're going to have to call the ball in the pocket every time, and call it perfectly. Fewer people will migrate to new nodes because that [choice] might drive them out of business." Eng: "What we're looking at here is a phony economy - one where a bunch of investors fueled development and purchases. That created the Bubble, which created the temporary state of imbalance that we're in right now. Economics always alternate between periods of expansion and consolidation. Market development, meanwhile, is always chaotic, emotional, and often associated with irrational behavior." Janac: "The cost of glass is what is going to pull us out of this. There are 300 million TVs in this country, which will be replaced by LCD monitors. That is, when the cost of that monitor drops to $299 - in other words, less than a [conventional] TV." Eng: "When they stop broadcasting analog TV, that will make it [happen even more quickly]." Ford: "Right now, we're clearly seeing far more activity in the consumer store - cell phones, TVs - than we are seeing sales related to routers and switches. There's so much capacity right now in fiber, we got enough for years to come." Janac: "Meanwhile, we're seeing a completely different way of building companies. In the 1990's, investors didn't care about profitability. Think about it - how many quarters did you really need to go public?" Ford and Eng, together: "Zero!!!" Ford: "in 1999/2000, we did essentially 5 years' worth of IPOs in 15 months. It's going to take a long time to grow back to that level [of insanity] again. Meanwhile, it's the 'old school' economy once again. It's how you run your business. And, it's really foolish for anybody to be planning for an upswing. Nobody should be walking around this valley assuming that lower margins alone are going to get them back to profitability. We've all got to be watching our costs very, very carefully from here on out. We'll have better times, and wealth will be created once again, but the bottom line will be much more final going forward." Eng: "There's no doubt the Bubble was bad for business, but great for technology. We'll never again, in our lifetimes, see such a concentration of human capital and investment capital concentrated in one place [as we saw in Silicon Valley in the 1990's]. But the real legacy of the Bubble is not the human suffering or tragedy. The real legacy is the vast infrastructure that was built up [with all of that investment]. We're benefiting from that infrastructure now. We've got e-mail, shopping on-line, downloading lots of stuff - free stuff, X-rated stuff, pirated software - all of that and more. From that perspective, the Internet is just at the beginning." Ford: "Clearly with all of this, we don't really need 65 nanometers. There's lots of bandwidth waiting to be used in what we've got right now. But that doesn't mean innovation will stop." Eng: "What we have today are the consequences of the investment of the last decade. We've got data-video-voice technology. We've got communication-compute-entertainment technology. And we've got biology-medicine-electromechanical technology. Most importantly, we've got the silicon knowledge and the infrastructure to build on all of this. The best is yet to come." (Editor's Note: Thanks to VitalCom PR for facilitating this conversation. Thanks to John Ford, George Janac, and Tommy Eng for their willingness to speak with candor on the record.) Industry News - Tools & IP Applied Wave Research, Inc. (AWR) announced the Analog Office design suite, which the company says is targeted at "next generation analog and radio frequency integrated circuit (RFIC) designs, focused on total RF closure." The company also says this is the first complete IC design system introduced in over a decade that is "specifically architected and optimized for analog and RFIC designs," and that the design suite is integrated into existing digital and mixed-signal IC design flows. AWR is taking on several large industry players with this introduction and says in the Press Release, "Analog Office software is an RF-aware design methodology built around the Intelligent Net (iNet) technology. Unlike existing 'net' constructs built on a 'digital-centric' data model, iNet technology is an RF-accurate net model addressing multiple levels of abstraction, including an ideal 'short-circuit' model, a lumped element model, a fully distributed transmission line, and a full 3D EM model. iNet technology provides concurrent and real-time connectivity information between the schematic and layout representations, and eliminates the need for a serial post-layout connectivity extraction step. Full control of simulation and analysis can be applied to iNet technology, in the same manner as is applied to all other devices in the design for complete RF design closure. Then the Analog Office system addresses high-frequency impairments that force the need to obtain complete 'RF closure' between the RFIC's system and circuit, electrical and physical, and design and test activities before commitment to IC implementation." Aldec, Inc. announced that its Active-HDL version 6.1 now supports C synthesis through its interface with Celoxica's DK2 Design Suite. The companies say that by adding support for Celoxica's C-based FPGA synthesis tool, system designers are now able to support VHDL, Verilog, C/C++, and Celoxica's Handel-C from a common, unified environment. Designers can use Active-HDL's design entry environment to develop code, and then invoke both HDL and C synthesis tools directly from its Design Flow Manager. Also from Aldec - The company announced that Amirix Systems Inc.'s recent embedded design with 6+ million FPGA gates was accelerated over 16x using Aldec's hardware acceleration product, Riviera-IPT. While developing the design, Amirix says it previously simulated the design for three days in regression testing to confirm system-level functionality, but condensed verification time from three days to less than five hours using Riviera-IPT. And this from Aldec, as well - The company announced that PnpNetwork Technologies, Inc. completed an ASIC core chip for a terrestrial reception set-top-box using Riviera-IPT to accelerate verification runs. The performance increase from "days to hours during project development" was primarily realized during the RTL debug stage, according to the companies where many of the design's small iterations previously created bottlenecks for simulation times. Altium Ltd. announced the release of a new TASKING embedded software development toolset for the TriCore architecture that includes next-generation Viper compiler technology. Altium reports that internal benchmarking has shown increases in execution speed and decreases in code size of an average of 10%, compared to the previous TASKING TriCore toolset. The company also says, "The new toolset excels in performance of generated code, completeness of features, architecture support, and compliance with industry standards. The new toolset has been extensively tested to ensure compatibility with all leading third-party TriCore products." Ansoft Corp. announced that it has upgraded its Maxwell Equivalent Circuit Extractor (ECE), which will allow users to extract lumped parameter circuit models directly from Maxwell to SIMPLORER. The company says new ECE features include mechanical pins used for linear and rotational models, rotational models that can use either angle or speed, the ability to edit coil resistance and turns in SIMPLORER, and the ability to assign extra ports to physical domains. ARC International announced that Altek has licensed an integrated development platform for use in product development, including the ARCtangent processor, the MetaWare Software Development Tool Suite, and the MQX/RTOS. Atrenta Inc. introduced SpyGlass LP to optimize designs for low power by allowing users to create "power-efficient RTL" early in the design cycle, and eliminate many iterations now required to optimize for power consumption later in the design cycle. The product provides guidance for low power techniques targeting dynamic power, leakage power, and voltage management issues. MIT's EECS Professor Anantha Chandrakasan, said, "In order to get power efficient designs, low-power techniques need to be incorporated from the beginning. The quality of RTL code is very important for downstream optimizations targeting lower power designs. Atrenta's predictive analysis techniques can help create power efficient RTL and enable designers to deploy their low power design methodology." Cadence Design Systems, Inc. and AsusTeK Computer Inc. announced that AsusTeK has selected the Cadence SPECCTRAQuest design and analysis product for its ultra-high-frequency, high-speed PCB motherboard designs. AsusTeK says its design team used SPECCTRAQuest for PCB development for simulation analysis and constraint-driven layout, provided that thorough solution-space analysis has been performed. Also from Cadence - The company announced the release of the Cadence Virtuoso Chip Editor chip finisher, which uses the OpenAccess API and database to directly link the Cadence Encounter digital platform with the Cadence custom environment, a development which the company says provides customers with upwards of 10x performance and 3x capacity for digital and mixed-signal designs. Chip finishing is the final stage of design implementation and has traditionally required the exchange of multi-gigabyte data files (for example, DEF or GDSII formats) between digital and custom environments - a slow process. The new Virtuoso Chip Editor uses the OpenAccess database to eliminate the file-transfer bottleneck. From Cadence, as well - The company announced that several additional companies, including ARM and NVIDIA Corp., have selected the Cadence Incisive verification platform for nanometer-scale IC development. The company says the new platform provides up to 100x more "full-chip performance" than RTL simulation, and that seven companies chose the platform in the first quarter of availability. Finally - Cadence Design Systems, Inc. and MatrixOne, Inc. announced a strategic alliance to produce a "suite of product lifecycle management (PLM) solutions." As part of the alliance, technologies from both companies will be combined to create "new collaborative design, component supplier management, and design-for-supply-chain solutions." Cadence says that technologies acquired from SpinCircuit and the Thales Group will be integrated with design data management, change management, and collaboration technologies from MatrixOne to create products that will integrate with Cadence's electronic design products and MatrixOne's enterprise PLM offerings. Both companies says the their new offerings will support open integration with a wide range of third-party tools. Meanwhile, in closely related news - Cadence Design Systems, Inc., MatrixOne, Inc., and IBM announced during a joint May 21st webcast that they are teaming together to deliver a "comprehensive, integrated set of PLM solutions for the global electronics industry." Dave DeMaria, Executive Vice President of Cadence Systems Solutions, said that this type of offering has never existed in the electronic market before, although he acknowledged that it's a very well known strategy in the mechanical world. Whether you agree that this type of offering is new or unique, Cadence believes "this new class of problems associated with collaborative design" will be solved by application of the integrated offerings from the three companies. Specifically, the Press Release said, "The new offerings will combine business transformation consulting, application customization, installation, and training from IBM Global Services; platforms and software - including IBM WebSphere and DB2 middleware products; along with new, integrated PLM offerings from Cadence and MatrixOne (mentioned previously). This advanced solution will enable collaborative design directly from the engineering desktop, synchronize activities across the software, electronics and mechanical design disciplines, and make it easier for original equipment manufacturers (OEMs), semiconductor companies and Electronic Manufacturing Services (EMS) providers to work together." Not surprisingly, as part of this plan, Cadence, MatrixOne and IBM Global Services are "working with customers, other vendors, and industry groups to develop and support new standards to improve integration and interoperability across the key technologies used in the software, electronic and mechanical design disciplines." Meanwhile, most of us weren't waiting for Cadence, IBM, and MatrixOne to tell us that the semiconductor industry is no longer vertically integrated -and it's simply not plausible that Cadence, IBM, and MatrixOne have now just spotted the problems that arise from disaggregation in the market. But nonetheless, by throwing their core competencies at the problems in this carefully choreographed manner, the three companies may have hit on something here. The long list of advantages enumerated during the joint webcast include: - Effective work in progress design management software - Timely collaboration between sourcing and manufacturing - Library and data management - Collaboration around Bill of Materials - Integration into a company's enterprise management tools - Configured to be added to company's infrastructure - Ease complexity of collaboration across various corporate firewalls and companies with divergent core competencies. - Secure high-volume data exchange - Efficient change management across the design chain No doubt, the joint announcement and the strategic thinking behind it, does knit together a variety of concepts and technologies to create a rational fabric for design, collaboration, and increased product development and manufacturing efficiency. Don't think for a minute, however, that they're not going to have a lot of competition in this arena. There are similar offerings addressing all the various parts of this equation in existence today emanating from a plethora of companies. It will only be a matter of time before some subset of those diverse offerings are similarly knit together via corporate joint ventures to take on the triumvirate announced on the 21st. Celoxica Ltd. announced support for the 90-nanometer Spartan-3 FPGAs from Xilinx, Inc. The companies said that by combining the Celoxica DK Design Suite with platform FPGAs such as Spartan-3, designers can efficiently implement high-density, low-cost programmable systems that include millions of gates and soft processor cores, including Xilinx's MicroBlaze. Additionally, Celoxica announced that Chunghwa Telecom Co., Ltd. has adopted Celoxica's DK Design Suite and RC2000 development boards. Chartered Semiconductor Manufacturing and Mentor Graphics Corp. announced a collaboration to deliver IC analog/mixed-signal (AMS) design kits validated for various Chartered manufacturing processes, starting with 0.18 micron and then extending from 0.13 micron to 90 nanometer. The Mentor AMS design kits are available at no charge and allow the IC design workflow to be tailored for the Chartered RF CMOS process. The kits provide all foundry data files and models for use with front and back-end IC design tools from Mentor Graphics. Designers can work within Mentor's AMS tool flow, or move between Mentor's Calibre design platform and front-end design products from other EDA providers. CPU Technology, Inc. and Magma Design Automation announced they have signed a long-term licensing agreement for Magma's physical design tools. The companies say the licensing agreement will allow CPU Tech to adopt a COT model for its deep-submicron SoC designs. CPU Tech will interface its front-end, system-level modeling and design tools to Magma's back-end placement and routing tools. Emulation and Verification Engineering (EVE) announced that Canon Information System Research of Australia (CISRA) has chosen ZeBu, EVE's verification platform, to verify and debug a new line of ASICs. CISRA says it evaluated ZeBu over a one-week period, using existing design, and used it to co-simulate HDL testbenches, thereby reducing regression testing time. CISRA is now migrating HDL testbenches into C++ transactors with ZeBu. Future Design Automation announced SystemCenter, which is a suite of co-development software tools for high-level software and hardware design and verification. The company says the new suite increases the productivity of DSP designers, algorithm developers, system architects, hardware designers, and verification engineers developing SoC that include complex algorithms. (Rhetorical question: Are there any SoCs that don't include complex algorithms?) Using the suite, system architects can take functionality created by software designers, create hardware architectures, and transfer the design to hardware designers for implementation in standard HDL environments. The company notes that all of these engineering disciplines can use the original C source code as a reference specification. InnoLogic Systems, Inc. announced that Fujitsu used the company's ESP-CV functional verification offering to meet production delivery deadlines for Fujitsu's Mobile FCRAM (Fast Cycle RAM) burst mode devices. Mentor Graphics Corp. announced what the company describes as a comprehensive FPGA design flow that "expands traditional FPGA tools with new technologies to address emerging challenges of complex FPGA designs." The three-part flow extends from high-level FPGA design through PCB design, and includes "existing and future technologies" for the design and verification of the FPGAs, embedded systems, and PCBs containing FPGAs. Walden C. Rhines, Chairman and CEO of Mentor Graphics, sounded the trumpets for "existing and future" battlefronts when he said, "We're advancing our position in FPGA design by building beachheads around our tools that are de facto standards in their respective markets." Meanwhile, the company says it will continue to deliver new tools and enhancements to existing tools that address FPGA design/verification, embedded systems design/verification, and PCB system design/verification. Meanwhile - Mentor Graphics Corp. and Royal Philips Electronics announced a technology collaboration to help their mutual customers implement high-speed USB in embedded applications. The two companies says they are working jointly to create USB 2.0-compliant combinations of transceivers and IP, in the hopes that "proven interoperability will help customers by reducing risk, shortening development times, and lowering overall system development costs." To date, Philips has used the Mentor Graphics USB IP reference platform to achieve compliance certification of the Philips UTMI Transceiver, ISP1503. Finally - Magma announced that Goyatek Technology Inc. has implemented the first 0.13-micron SoC design in the greater China region using Blast Fusion and Blast Noise. Model Technology, which is a Mentor Graphics company, announced the availability of its HDL simulator, ModelSim for Linux, running on Intel Itanium 2-based platforms. Mentor says it is the first EDA company to support the 64-bit Intel processor. Engineers from Intel and Model Technology report that they worked together to ensure "optimal performance while preserving the unique advantages of the ModelSim product." Guru Bhatia, Director of IT Engineering Computing at Intel, said, "We are excited to see the ModelSim software product line from Model Technology on Intel Itanium 2 processor-based systems, offering the best-in-class 64-bit computing performance. This [tool] offering reinforces that the Itanium 2 processor is a feature-rich, stable, and easy-to-use high-performance 64-bit computing platform for developing and running mission-critical CAD applications for silicon design." It'll probably do the trick, as well, if the application is just important, but not quite mission critical. MIPS Technologies, Inc. announced that Wintegra Inc. has introduced two new additions to its 64-bit MIPS64 5Kc-based range of products for DSLAM systems. The WIN717D4 and WIN717D6 are designed to meet price, features, and performance requirements in small DSLAMs (24-48 ports), and are subsets of the WIN737. Additionally the two news products come with a range of communication protocols that are "royalty free and production verified." OEA International, Inc. announced a major update to its SPIRAL 3D-inductor design toolset for synthesizing embedded spiral inductors in analog and RF chips, hybrids, MCMs, and PCBs. The toolset can be used in batch mode, as a stand-alone UNIX GUI, or from within the Cadence DFII environment. If SPIRAL is used from within the Cadence framework, it automatically generates layout, schematic, and symbol views. New SPIRAL features include refined substrate modeling capability, support for various numbers of parallel metal layers in the winding or cross-under, and automatic generation of patterned ground shields. RF Engines Ltd. announced the company has added high-speed polyphase DFT (Discrete Fourier Transform) cores to its DSP technologies IP. The company says these are the world's first polyphase DFT cores to be available as standard licensable IP that are fully characterized and ready to use off the shelf. Sagantec announced Anaconda, which the company calls "a schematic-driven, constraint-based compaction tool that accelerates analog physical design by automating repetitive manual layout tasks and enabling analog design reuse." Specifically, the tool intends to replace the manual effort required to correctly place and size the layout details of derivatives and variations for a given physical topology. Anaconda is described as a "correct-by-construction" tool, which reads sizes and constraints from a schematic and then refines the topology to automatically implement the specifications, checking symmetry, wire widths, matching, alignment, and correct design rules. Anaconda is integrated with Cadence's Virtuoso XL design system. Silicon Canvas, Inc. (SCI) announced that KeyEye Communications has selected Silicon Canvas Laker for its KX5002 (and future) communication chip designs. The company says it will use Laker for creating analog blocks, chip assembly, and post-place-and-route DRC violations location and repair. KeyEye has established a production design flow with Laker, which has allowed the company to add advanced automation capabilities to the process. SynaptiCAD announced that it has upgraded its DataSheet Pro and TestBencher Pro products to include multiple graphical displays that will enable the user to open and edit several timing diagrams simultaneously. The company says the new feature is useful for visually comparing different timing diagrams. Users can also view one timing diagram while drawing a similar timing diagram in the design. DataSheet Pro also provides a full timing analysis environment that can be used during the design phase. The timing diagrams created by the engineer can include both digital and analog signals, with full support for advanced documentation constructs such as time breaks, grid lines, super and subscripted text, and active-low signal names. These timing diagrams can later be transferred to the documentation department for direct incorporation into component data sheets . Summit Design, Inc. announced a new assertion-based verification flow, based on the PSL/Sugar language. The company says the new flow combines Summit's Visual Elite and IBM's FoCs tool and should be used to accelerate HDL and SystemC design and verification. Assertion-based verification allows designers to define high-level functional rules (assertions or properties) that can be carried along the design process, and to identify errors and missed coverage at multiple levels of abstraction. Visual Elite is a C/C++ and SystemC functional modeling and verification environment with which engineers capture and analyze complex hardware architectures, and map them to RTL implementation. FoCs takes Sugar assertions and transforms them into assertion checking code, which can then be integrated into the simulation environment. The combination of FoCs and Visual Elite provides for dynamic assertion checking, which Summit says improves verification effectiveness. Also from Summit - The company announced the availability of Visual Elite 4.0, with major enhancements including Visual Elite Embedded System Co-design (ESC - a SystemC solution for target processors), SystemC fast simulation and coding style utilizing FastC (a native SystemC text environment), and several "advanced" verification and debugging mechanisms. Guy Moshe, President and CEO at Summit, said, "Our SystemC and C/C++ technologies, and expertise, have grown our development environment from a standard SystemC flow into a more powerful system-design solution, with many of the needed components that are essential for our customers in a real system (HW/SW) design flow. We offer not only language support, but also a real toolset that can serve multiple design paradigms, and multiple verification domains." The company added that Visual ESC offers high-level functional and architectural design analysis and exploration in the context of target architectures from Xilinx, ARM and, Motorola. TNI-Valiosys and Verisity Ltd. jointly announced the availability of a flow in which TNI-Valiosys' imPROVE-HDL static property checker is interfaced to Verisity's Specman Elite testbench automation tool, which the companies say combines static property checking and testbench automation to boost the quality and reduce development time for SoCs. Virage Logic Corp. announced that ATI Technologies Inc. has chosen Virage's Area, Speed and Power (ASAP) Memory High-Density (HD) embedded memories for its RADEONTM 9200 chip series. The products were produced on UMC's 0.15-micron LV process. WaferYield Inc. has introduced WAMA 2.7 release with new features for the WAMA Test module. The new features intend to enhance Prober throughput and functionality, reduce operation time, and save on manufacturing resources while maximizing yield. The company says that placement of the reticle array on the wafer has a significant impact on yield, throughput, product reliability, and profitability. WAMA algorithms generate an optimized map for placing dies/fields on a wafer - a function performed by a multi-dimensional analysis, taking into account the range of parameters which impact on yield. WAMA analyses this data and generates precise yield probability predictions for each area on the wafer. The output is an optimized wafer map that instructs the Stepper/Scanner to maximize the number of dies printed in certain areas, which meet the pre-specified yield threshold. Then the Prober is instructed to avoid testing dies in areas that have low yield probability. The company says that printing and testing only dies with high yield probability can save time and resources and eventually increase fab productivity and profitability. X-FAB Group announced a new development that the company says makes photodiodes for analog applications available to its customers for the first time. The new photodiodes - based on native CMOS diodes - have a spectral sensitivity comparable to the human eye and, furthermore, are suitable for infrared applications. The foundry's process options include the integration of the photodiode and circuit onto one chip, which allows electronic devices to receive several concurrent signals, including weak and noisy ones. The process also enables high data transfer rates. An optional anti-reflective coating reduces the loss of light energy to a minimum and requires only marginal process modifications. The company says that infrared applications are well suited for photodiodes, such as intelligent light barriers or sensors for position control. Coming soon to a theater near you SystemVerilog Class - Stuart Sutherland of Sutherland HDL is teaching a half-day SystemVerilog class on May 27th in San Jose, CA. If you attended the SystemC class mentioned last week, you'll want to round out your education by attending this one as well, in order to see what's what and compare the technologies. Sutherland is member of both the IEEE 1364 Verilog standards group, where he serves as the chair of the PLI task force, and the Accellera SystemVerilog standards committee, where he serves as the editor for the SystemVerilog Language Reference Manual. The upcoming seminar will be taught twice on the 27th in San Jose, CA - once in the morning and again in the afternoon. Meanwhile, Stu and I are going to record an audio interview in the next several days that will be available on edatoolscafe.com straightaway. I hope you'll listen in to hear our conversation when it gets posted to the website. ( www.sutherland-hdl.com ) EDA Executive Business Forum at DAC - Armstrong Kendall, Inc. has announced the program and speakers for the 7th annual EDA business confab, this year featuring CMP's Paul Miller and D.A. Davidson & Co.'s Bill Frerichs. (Other sponsors include EDAC, Lanza techVentures, and the Market Statistics Service.) Miller will be revealing the results of an EE Times EDA tool-users survey ("Pick me! Pick me!" they cry.), while Frerich will be interviewing AMD's Fred Weber, NVIDIA's Chris Malchowsky, and Pixelworks' Allen Alley to find out how things are faring in business and collaboration across the semiconductor food chain these days. The Forum is being billed as an "exclusive event" - and even if Woody Allen says, "I wouldn't want to belong to any club that wanted to have me as a member," you should plan to be there anyway. It's all happening on DAC Tuesday (June 3rd). More importantly, this event is just one part of the larger day-long DAC Management Forum on DAC Tuesday, designed for managers and executives, which debuts this year at the conference, co-sponsored by the Fabless Semiconductor Association (FSA). ( www.fsa.org and www.akipr.com/edabf ) Outsourcing Panel at DAC - To further discussion that might be prompted by this week's joint announcement with IBM and MatrixOne, Cadence is sponsoring "Outsourcing Design: A Good Thing or a Bad Thing?" - a panel discussion moderated by Mike Santarini of EE Times on DAC Monday. Dataquest's Gary Smith, Synopsys' Glenn Dukes, eSilicon's Mike Gianfagna, IBM's Karla Reynolds, Cadence's Paul Estrada, and LSI Logic's Ronnie Vasishta will be the panelists. This panel will explore where outsourcing is a good solution and what makes for good outsourcing partnerships. If these guys can't address those issues, nobody can. ( www.dac.com ) SAME 2003 - The Sophia Antipolis forum on MicroElectronics will be in its 6th year and will include a series of conferences and tutorials that explore state-of-the-art developments in the field of design and manufacturing of ICs and systems. Organizers say that the Executive Panel and CTO Panel will feature debates on key themes and will include international experts from the microelectronics sector. All told, there should be 850 participants, 40 speakers, and 35 exhibitors at the 2-day event. The event will take place in Sophia Antipolis, France, on October 8th and 9th. ( www.same-conference.org/ ) Newsmakers New book from Grant Martin and Henry Chang - Grant Martin, Fellow at the Cadence Berkeley Labs, and Henry Chang, Director of Cadence's Strategy Group, have edited a new book, Winning the SoC Revolution: Experiences in Real Design. The 11 chapters are written by numerous well-known voices in the industry and cover a range of topics including the recent history of the SoC, relevant design methodologies, IP use, design reuse, implications of emerging FPGA technologies, the non-technical issues surrounding collaborative design and team integration across various design paradigms within a SoC project, and case studies from Philips, TI, IBM, ARM, Xilinx, and Altera, among others. The text is readable and accessible - and more importantly, there is ample discussion of crucial concepts including platform-based design, verification, software/hardware partitioning, and system-level integration. The opening chapter by Martin has added appeal as he attempts a one-to-one mapping between the French Revolution and the SoC Revolution. But the not-to-miss chapter is from John Cohn at IBM, which closes the book. Cohn articulates the current state of the art in SoC design and lays out the far-ranging challenges facing the future of the technology. All told, if you can take a day or two to read this thing from cover to cover, you'll be ready to attend DAC. The book will be available at the Kluwar Press table in Anaheim. ChipMD Inc., a newly announced EDA company, has opened its doors in Cupertino, CA, and joins the industry just in time for DAC. Dale Pollek is founder, CEO and president. Ken Maples is Vice President for Customer Support, and Ravi Ravikumar is Vice President for Business Development. In addition, Gary Larson is the Chairman of the Board. These fellows have 20+, 25+, 20+, and 30+ years' experience in EDA, respectively. The company says it will be selling tools that function at the design stage with the intention of improving yield at the manufacturing stage. The company also says its technology is already in production use by system and circuit designers in communications, computers, automotive, and consumer electronics markets Critical Blue - As an additional indication of growing optimism in this industry, yet another EDA start-up has been announced. Critical Blue, formally launched on May 12th in Edinburgh, Scotland, will be offering its Cascade Tool Suite. The company says Cascade consists of a set of "unique co-processor synthesis tools that accelerate software in embedded microprocessor applications. It analyzes application software on the main microprocessor and, under the control of the user, automatically synthesizes a hardware co-processor specifically designed to accelerate software tasks selected by the user." The company points out that Cascade is neither a system-level hardware/software-partitioning advisor, nor a traditional configurable microprocessor platform, but rather a co-processor synthesis tool suite that provides hardware designers with a "true hybrid" between hardware and software. David.Stewart, Founder and Vice President Sales and Marketing, said, "If customers can build into their products a level of flexibility that will allow them to make minor modifications to the product in the field, they'll have a solution for faster time to market. Meanwhile, we're delighted to have [industry guru] Simon Davidmann joining our Board of Directors. Simon knows we're addressing a market need here that's particularly important at this moment because of the tough economic climate." "Of course, you could ask why we need another EDA company. I don't think the big EDA companies can be relied on to come up with the next generation of tools to get customers to the next level of innovation. The big companies have enough problems just keeping their existing customers happy and dealing with technology migrations. They don't have the space and freedom to explore new areas and come up with the solutions that we're coming up with. When they do add technology that moves the industry to the next level, it's through acquisition." Stewart makes a compelling case - this company may very well be one of those worth watching going forward. Meanwhile, Luigi Mantellassi, Imaging Division Processors R&D Director at STMicroelectronics, is quoted in the Press Release: "We have recently tested the technology of Critical Blue and the initial results look very promising in terms of the performance/cost ratio and the development time we would have expected using traditional methods." Mentor Graphics Corp. announced a technology alliance with STMicroelectronics, which the companies say, was created to address the needs of today's analog/mixed-signal (AMS) and radio frequency (RF) designers. Mentor and ST have created a common R&D team with the goal of maximizing AMS and RF design productivity for the companies' mutual customers, as well as internal ST design teams. The alliance announcement said, "The alliance is another significant outcome of five years of cooperative effort between the two companies. Through the development of comprehensive VHDL-AMS model libraries and the integration of the Mentor Graphics AMS design and verification tools into STMicroelectronics' design kits, the two companies are developing methodologies to shorten design cycles and increase first-pass design success for AMS and RF designers." This should be an interesting alliance to watch over the next several years. Also from Mentor Graphics - The company announced that Patrick McManus has joined the company's Board of Directors. McManus retired recently from Charles Schwab as Senior Vice President of Finance. Previously, he held executive-level finance and management positions at companies including Pacific Express Airlines, Acurex Solar Corp., Itel Corp., and Univest Venture Capital. McManus has an MBA from Stanford University and a BA from Dartmouth. TriCN announced the appointment of Dale Olstinske as Vice President of Sales. Olstinske has 25+ years' sales and management experience in the semiconductor industry. He has a BSECE from the University of Wisconsin, started his career at Intel, served in various roles at Marten, LSI Logic, and Frequency Technology, and most recently was responsible for growing worldwide sales revenue at LogicVision through the period of that company's IPO. PSL/Sugar Consortium - Organizers says that the widespread adoption of the property specification language PSL/Sugar for assertion-based verification has prompted 15 electronics and EDA companies to announce initial steps in the formation of the PSL/Sugar Consortium. The new international organization will be chartered to help hardware designers adopt and implement PSL/Sugar and its methodologies to speed design verification. Founding members include: 0-In Design Automation, Inc., @HDL Inc., Cadence Design Systems Inc., IBM Corp., Novas Software, Inc., Real Intent, Inc., Ricoh Company, LTD., Summit Design Inc., SynaptiCAD, Inc., Tharas Systems, Inc., TNI-Valiosys, TransEDA PLC, Verisity Ltd., Veritable Inc., and Verplex Systems Inc. In the category of ... Is it just me, or are we all really cranky just before DAC? I received an e-mail this past week in response to last week's monster issue on Linux et al, describing in detail how the newsletter needs to be abbreviated to meet the needs of the readership. Since this newsletter is done as a courtesy to the industry and provides a (perhaps flawed, but) much needed editorial platform for companies who are short on such during these barren and forlorn days in technical publishing - I'm not going to reduce the amount of content right now, particularly just prior to DAC. Many companies want to have their say, yet few have places within which to say it. Having said that, here are four more companies speaking at my request on four more Issues at DAC. These are not intended to be detailed tutorials on topics, but a bit of constructive commentary as run-up to the substantive discussions that will no doubt take place in Anaheim. Two weeks ago, we heard about Power, and SystemC versus SystemVerilog. Last week, we heard about Revitalizing EDA, and Structured ASICs. This week's discussions include Consortia for R&D, Design for Yield, FPGAs, and Analog Design. Next week, in the DAC issue, we'll hear about Memories, Design for Manufacturing, Test, and 90 nanometers. Meanwhile, if all of this content is too much for the busy reader - I have a suggestion. Please read the bits that are of interest to you and skip the rest. Thanks. Issues at DAC - Consortia for R&D The Invest in Sweden Agency (ISA) was established in 1995 by the Swedish government to help attract and facilitate foreign direct investment in Sweden. Rolf Rising is Director and Head of IT and Electronics for the Agency and during a recent phone call, offered this description of the SoC research and education underway there. The idea of governments working together with industry and academia to sponsor R&D has always been an interesting one. Here are Rising's comments on how that's happening in Sweden. "Socware Design Cluster, which is headed and promoted by ISA, was established in 2000 as a consortium between the three main universities in Sweden (Linkoping University, Lund University and Royal Institute of Technology) and the Acreo Research Institute for Microelectronics. These four entities decided to team up with ISA and invest in a public infrastructure for research into SoC design, which they appropriately saw as a crucial core technology for the wireless industry - which is, in turn, an industry that has been pivotal for the economic health of Sweden. Just look at Nokia and Ericsson, if you doubt that." "The Socware Design Cluster then successfully arranged for government sponsorship as well - along with funding from other authorities and foundations interested in the technology. The program was structured to fund a new Masters program and new Ph.D. research projects. In addition, funds where made available for industry partners to join or initiate special research projects. Industry partner investments are rewarded with access to any IP that might emerge from the project. Such IP can be used in any products the company chooses to use it in, but can not be resold as a stand-alone product." "Our initial emphasis was on education. We started in 2000 with 50 students in our Masters program, but this year expect up to 200 students - all working toward an advanced degree in engineering with an emphasis on system-on-chip design. Besides this, we have 70 Ph.D. students. Approximately 50% of our students are from other countries, in particular India and China. However, all of our students come out of the program well prepared to address the technical challenges associated with system design, in particular the RF and embedded software issues that are pivotal to wireless chip sets." "We are not concerned about expending energy educating foreign students. When the economy is strong, the students often settle here in Sweden and add to our technical brain trust. We also receive great benefit from our talented Ph.D. students. However, even if the students return to their home countries, we consider our efforts to be worthwhile as we believe these graduates become permanent good will ambassadors for Sweden." "Meanwhile, we know there are lots of companies who want to be part of our 'Wireless Valley' in Kista - where there are 25.000 people focusing on wireless system design - but some companies may not be ready yet to invest in the Socware Design Cluster. So we are able to offer them a position in various Research Demonstrators hosted by the Institute, and created from various Ph.D. research projects - projects such as software-defined radios, for instance, designed to integrate a transceiver front end for multi-mode and multi-standard applications." "For such companies, the Institute may recruit and incubate a professional team for a certain period until the team knows 'how to fly' - and then the company takes over. The Institute, therefore, acts as a gateway, which offers support to international companies wanting to invest in our emerging Socware Design Cluster." Issues at DAC - Design for Yield ChipMD has just opened its doors, and the staff is understandably riding high on the adrenaline associated with a new start-up. Dale Pollek is CEO of the new company and says that the focus of the soon-to-be-released tools will be one of the crucial problems in analog and mixed-signal design - Design for Yield (DFY). Ravi Ravikumar is Vice President of Business Development for the company. I spoke with both of them last week as they helped to distinguished between DFY and DFM (Design for Manufacturing). Pollek said, "Current solutions in DFM are focused very late in the design flow; starting from post layout and extending into the manufacturing steps. Yield is usually only considered after the first silicon is manufactured. DFY is distinguished from DFM by the fact that it forces designers to think about yield issues in their products at the very start of the IC design process. Yield is an IC-sensitive issue for all designs, whether pure digital, memory, mixed-signal, or pure analog/RF. At 130 nanometers and below, for instance, you might have 20 different possible types or layouts of transistors, each reacting differently to operating conditions and process parameters, such as temperature, voltage, oxide thickness, etc. You need to know in advance how these different design choices would function in real-world operating conditions in order to adjust your design parameters and maximize yield, before you cut your first masks." "How do you do that? You examine the process data that's readily available from your fab process people for your particular process technology, which gives you a fixed operating window for the device under development. Then, in order to make sure your device will deliver to specifications across all the combinations of these parameters and conditions, you need to reduce the impact of it all on yield. With the number of parameters involved, the traditional 'four corner' worst-case analysis will not provide you all of the key worst-case conditions. So, you must think out of the box." "Typically, designers are forced by time to market pressures to complete a design quickly - and design for yield is seldom a consideration until after first silicon. Then the design is rushed into manufacturing without fully considering the impact of the process. Some call this 'throwing the design over the wall' into manufacturing. Today's reality is such that time to market pressures require this strategy. Meanwhile, the complexities of understanding manufacturing issues have simply been too difficult to provide to design in a feasible method." Ravikumar said, "So we want to promote DFY by remembering that each circuit is required to operate within a specified operating region, which is in turn governed by pre-defined parameters such as voltage, temperature, etc. The circuit is then designed under the default or nominal process, voltage and temperature conditions - also known as the nominal operating point. Designers then do the traditional 'four corner' worst-case analysis to increase their confidence that the device will operate in the entire feasibility region. Implied in this is the fact that the operating region of the design and the feasibility region of the process technology used will match, to create a functional design across the entire range of parameters. Designers don't usually think about the process technology used - or yield - until after first silicon. Hence you see the problems with parametric yield." "DFY has almost always been an afterthought in design flows. This won't work anymore, now that masks are so expensive and development costs so high. Lost revenue and market share due to yield is at least an order of magnitude higher than these development costs. Lost yield is lost money. The typical design is set for the nominal process parameters that represent the ideal or golden processing conditions - but ideal conditions just don't exist in the real world." "Meanwhile, as process technologies emerge at 130 nanometers and below, you've got increasing process variations from die to die, lot to lot, and even high variances within the die itself, as you manufacture products. This means 'like parts' of the design may not actually perform 'close enough' to each other - a critical problem for dealing with timing, but even more critical in the RF/AMS world where you must have as close to matching results as possible. For digital designs, you might find you can just add larger guardbands and get to a working device. However, for AMS designs, you will need to keep within 3 sigma of the ideal conditions, to keep your yield adequate. In fact, some designs, such as large memories, will require you 'design in' up to six-sigma quality or beyond, as you can't afford one transistor to function differently when you have Giga-sized memories. Therefore, RF, analog and mixed signal design is most sensitive to all the DFY considerations." Issues at DAC - FPGA EDA Simon Bloch, formerly of Aristo Technologies, is now general manager of the FPGA Design Solutions division at Mentor Graphics Corp. in San Jose. He was willing to speak by phone for a few minutes last week and describe (with palpable enthusiasm) the future of the FPGA market and those vendors who are able to support it going forward. "After the merger, I continued to follow the FPGA market with great interest. I decided to join Mentor to focus on FPGA design because I saw the trend of designers choosing FPGAs in favor of ASICs and I felt that Mentor had the right pieces to appropriately service and grow the tool market." "We're all well familiar with ASIC and IC EDA. Now we're seeing that the FPGA EDA market is gaining momentum because of FPGA designs shifting to ASIC design approaches. There is a concern in the industry that the EDA industry will shrink if most IC designs move from ASICs to FPGAs. We, at Mentor, believe that the EDA industry will continue to grow, but we also believe that the FPGA EDA will grow at a higher rate." "Recent data on the FPGA industry from Gary Smith at Dataquest estimates the market size for the FPGA EDA market was at $100 million in 2001. We think that the 10,000 design seats of the serviceable FPGA market by EDA vendors will continue to require additional tools in the design flow and, as a result, the FPGA EDA revenue figures will grow 2x to 3x for us over the next few years." "Most of the FPGA tool budgets today are being spent on design creation, synthesis, and functional verification. However, with the increasing complexities of the FPGA devices from Xilinx, Altera, and Lattice, the need for additional tools is emerging. We believe the growth areas in the FPGA design will be in timing analysis, RTL debug, high-level synthesis, formal verification, design management, hardware/software co-design, embedded software design, and FPGA/PCB co-design." "The increase in usage of FPGAs is also driven by the fact that the crossover point between FPGAs and ASICs moves with every process generation. At 0.13-micron, the crossover point in terms of volume is between 50,000 to 100,000 units. Many ASIC-type applications are now being done in FPGAs because of lower up-front cost and lower risks. And that will become even more significant as we move to 90 nanometers." "So we're seeing that many companies are moving to FPGAs because the devices are adequate to meet design requirements. When FPGA implementations are feasible due to power and size limitation, engineering managers are usually asking themselves three questions to determine usability of FPGAs." "Does the FPGA have high enough internal clock rates?" "Does it have sufficient amount of high-speed I/Os?" "Does it have sufficient memory capacity?" "When the answers to these questions are positive, the design teams are selecting FPGAs instead of ASICs. If you look at the Stratix from Altera, or the Virtex-II Pro from Xilinx, these devices are large and powerful SoC devices that include multiple processors, tens of megabits of embedded memory capacity, can reach 400MHZ in performance, accommodate over a thousand of pins, and include high speed serial transmitters. In the face of all of this, complex FPGA design is going to dominate what used to be an ASIC design approach." "That means that design challenges will no longer be about synthesis and place-and-route. It will be centered on the dominance of interconnect delays, special clock domains, as well as links with HW/SW and PCB development. To maintain FPGA design productivity, we're going to see new tools at a higher abstraction level, tools that will verify functionality at that level and provide formal verification as well. Mentor is definitely going to address the flows of designing complex FPGAs." Issues at DAC - Analog Design Coby Zelnik , Senior Vice President of Business Development at Sagantec North America, Inc., weighed in on the world of analog design during a recent phone call. Zelnik noted, "It boggles the mind to think that, compared to the number of analog designs needed each year, current estimates say there may be no more than 4000 analog designers worldwide pumping out those designs - designs which are crucial to bringing a universe of products to fruition. Clearly, those analog design guys need help and that's what analog companies like Barcelona, ADA, NeoLinear, and Sagantec, among others, are trying to do." "The new generation of analog design tool offerings are meant to address the critical lack of productivity in layout and to promote design reuse and analog IP. Any tools that address that level of detail - and use correct-by-construction technology - are the ones that are going to help alleviate the problems in analog design. A successful tool has to be aware of all the layout details, some of which are quite subtle, and master them in a correct-by-construction manner." And what's the key to improving productivity in analog design and layout? Zelnik was adamant, "Automation! Analog design tools will automate and accelerate the tasks that people are currently handling manually - and all of us know that, even these days, most back-end layout is done manually. Automating that phase is what's needed to improve the overall process, to accelerate this half-art/half-science process. Of course, I don't believe in machines taking over the creative/artistic part of the job. EDA understands the need to accelerate the process without compromising the human creativity." "Meanwhile, Cadence continues to own the lion's share of the back-end process. Companies like Sagantec are not attempting to dislodge Cadence, but instead want to tie into existing flows and enhance the process by automating steps previously hampered by manual-only techniques." "Automating analog design is a technology that's still in its infancy. And, since analog designers see themselves as artists, they're not necessarily interested in incorporating automation into a design process of which they see themselves as a crucial part. Subsequently, we have a bit of an uphill struggle ahead to convince them that these tools will not strip them of an opportunity for creativity - but rather will give them an opportunity to enhance their creativity and artistry." "There may also be a generational issue here. The 'old school analog guys' have always crafted their analog designs lovingly, by hand, with the same care that calligraphers use with their lettering, for instance. Meanwhile, the 'new analog guys' today wonder why the analog process isn't more automated - like the digital process they're aware of." "To stretch the analogy a bit, the newer designers appreciate the craftsmanship of handcrafted calligraphy, but know that there's Old English font available [in Word] that'll do just as good a job for applications where lettering is needed. As the current generation of analog designers retires, and a new class of designers comes on-line, these new guys will look at analog as just another design function - just as they see digital and mixed-signal design today. Analog will still be a specialized art, but not a mysterious one. And it will be seen as an intrinsic component of the overall systems design process." "However, that doesn't mean that 'systems types' will over-ride 'analog types' anytime soon. In fact, the analog world is not going to change radically at all, for the foreseeable future. But even as we speak, we're starting to see whole new populations of analog designers in China, India, and Eastern Europe emerge. As opposed to the traditional designers in established markets, these newcomers may approach analog design problems with a new mindset. For them, it may not be as difficult to embrace automation." How should the industry address the shortage of analog designers? Zelnik said, "Analog design skills are still best learned on the job, not in a structured academic setting. Analog design is not something someone learns well, for instance, as an undergraduate. You have to get out and work among those who know how to do this stuff - and even then, expect to take a long time to master the skills involved. And that will still be true even when the technology behind automated analog design has fully matured." "At Sagantec, we believe that current analog design techniques and the people behind them are indispensable. EDA needs to accelerate their tasks and help them be more productive, but at the same time, preserve their skills and creativity. So we should be careful in what designers can safely delegate to automation software. The higher-level decisions regarding architecture and topology are best done by designers themselves, while the lower level details of geometric implementation can be done faster and more accurately via automation." (Editor's Note: Are you still reading? If so, don't bother to write and tell me that it was Groucho Marx, not Woody Allen. I was just checking to see if you knew. See you all at DAC!) --Peggy Aycinena is a Contributing Editor and can be reached at peggy@ibsystems.com . You are subscribed as: [dolinsky@gsu.by]. EDAWeekly is a service for EDA professionals. EDAToolsCafe respects your online time and Internet privacy. If you would prefer not to receive this type of email or if you consider this message as unsolicited commercial e-mail, please click here . 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